fsl-ls1043a.dtsi 22.4 KB
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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 * Device Tree Include file for NXP Layerscape-1043A family SoC.
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 *
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 * Copyright 2014-2015 Freescale Semiconductor, Inc.
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 * Copyright 2018, 2020 NXP
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 *
 * Mingkai Hu <Mingkai.hu@freescale.com>
 */

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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
	compatible = "fsl,ls1043a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

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	aliases {
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		crypto = &crypto;
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		fman0 = &fman0;
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		ethernet4 = &enet4;
		ethernet5 = &enet5;
		ethernet6 = &enet6;
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		rtc1 = &ftm_alarm0;
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	};

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	cpus {
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		#address-cells = <1>;
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		#size-cells = <0>;

		/*
		 * We expect the enable-method for cpu's to be "psci", but this
		 * is dependent on the SoC FW, which will fill this in.
		 *
		 * Currently supported enable-method is psci v0.2
		 */
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
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			reg = <0x0>;
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			clocks = <&clockgen 1 0>;
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			next-level-cache = <&l2>;
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			cpu-idle-states = <&CPU_PH20>;
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			#cooling-cells = <2>;
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		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
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			reg = <0x1>;
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			clocks = <&clockgen 1 0>;
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			next-level-cache = <&l2>;
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			cpu-idle-states = <&CPU_PH20>;
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			#cooling-cells = <2>;
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		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
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			reg = <0x2>;
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			clocks = <&clockgen 1 0>;
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			next-level-cache = <&l2>;
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			cpu-idle-states = <&CPU_PH20>;
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			#cooling-cells = <2>;
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		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
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			reg = <0x3>;
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			clocks = <&clockgen 1 0>;
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			next-level-cache = <&l2>;
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			cpu-idle-states = <&CPU_PH20>;
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			#cooling-cells = <2>;
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		};

		l2: l2-cache {
			compatible = "cache";
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		};
	};

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	idle-states {
		/*
		 * PSCI node is not added default, U-boot will add missing
		 * parts if it determines to use PSCI.
		 */
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		entry-method = "psci";
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		CPU_PH20: cpu-ph20 {
			compatible = "arm,idle-state";
			idle-state-name = "PH20";
			arm,psci-suspend-param = <0x0>;
			entry-latency-us = <1000>;
			exit-latency-us = <1000>;
			min-residency-us = <3000>;
		};
	};

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	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0 0x80000000>;
		      /* DRAM space 1, size: 2GiB DRAM */
	};

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	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		bman_fbpr: bman-fbpr {
			compatible = "shared-dma-pool";
			size = <0 0x1000000>;
			alignment = <0 0x1000000>;
			no-map;
		};

		qman_fqd: qman-fqd {
			compatible = "shared-dma-pool";
			size = <0 0x400000>;
			alignment = <0 0x400000>;
			no-map;
		};

		qman_pfdr: qman-pfdr {
			compatible = "shared-dma-pool";
			size = <0 0x2000000>;
			alignment = <0 0x2000000>;
			no-map;
		};
	};

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	sysclk: sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "sysclk";
	};

	reboot {
		compatible ="syscon-reboot";
		regmap = <&dcfg>;
		offset = <0xb0>;
		mask = <0x02>;
	};

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	thermal-zones {
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		ddr-controller {
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			polling-delay-passive = <1000>;
			polling-delay = <5000>;
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			thermal-sensors = <&tmu 0>;
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			trips {
				ddr-ctrler-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				ddr-ctrler-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		serdes {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 1>;

			trips {
				serdes-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				serdes-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		fman {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 2>;

			trips {
				fman-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				fman-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		core-cluster {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
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			thermal-sensors = <&tmu 3>;

			trips {
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				core_cluster_alert: core-cluster-alert {
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					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};
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				core_cluster_crit: core-cluster-crit {
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					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
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					trip = <&core_cluster_alert>;
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					cooling-device =
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						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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				};
			};
		};
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		sec {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 4>;

			trips {
				sec-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				sec-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
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	};

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	timer {
		compatible = "arm,armv8-timer";
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		interrupts = <1 13 0xf08>, /* Physical Secure PPI */
			     <1 14 0xf08>, /* Physical Non-Secure PPI */
			     <1 11 0xf08>, /* Virtual PPI */
			     <1 10 0xf08>; /* Hypervisor PPI */
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		fsl,erratum-a008585;
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	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <0 106 0x4>,
			     <0 107 0x4>,
			     <0 95 0x4>,
			     <0 97 0x4>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
	};

	gic: interrupt-controller@1400000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
		      <0x0 0x1402000 0 0x2000>, /* GICC */
		      <0x0 0x1404000 0 0x2000>, /* GICH */
		      <0x0 0x1406000 0 0x2000>; /* GICV */
		interrupts = <1 9 0xf08>;
	};

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	soc: soc {
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		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		clockgen: clocking@1ee1000 {
			compatible = "fsl,ls1043a-clockgen";
			reg = <0x0 0x1ee1000 0x0 0x1000>;
			#clock-cells = <2>;
			clocks = <&sysclk>;
		};

		scfg: scfg@1570000 {
			compatible = "fsl,ls1043a-scfg", "syscon";
			reg = <0x0 0x1570000 0x0 0x10000>;
			big-endian;
		};

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		crypto: crypto@1700000 {
			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
				     "fsl,sec-v4.0";
			fsl,sec-era = <3>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x00 0x1700000 0x100000>;
			reg = <0x00 0x1700000 0x0 0x100000>;
			interrupts = <0 75 0x4>;
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			dma-coherent;
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			sec_jr0: jr@10000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x10000 0x10000>;
				interrupts = <0 71 0x4>;
			};

			sec_jr1: jr@20000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x20000 0x10000>;
				interrupts = <0 72 0x4>;
			};

			sec_jr2: jr@30000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x30000 0x10000>;
				interrupts = <0 73 0x4>;
			};

			sec_jr3: jr@40000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x40000 0x10000>;
				interrupts = <0 74 0x4>;
			};
		};

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		dcfg: dcfg@1ee0000 {
			compatible = "fsl,ls1043a-dcfg", "syscon";
			reg = <0x0 0x1ee0000 0x0 0x10000>;
			big-endian;
		};

		ifc: ifc@1530000 {
			compatible = "fsl,ifc", "simple-bus";
			reg = <0x0 0x1530000 0x0 0x10000>;
			interrupts = <0 43 0x4>;
		};

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		qspi: spi@1550000 {
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			compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x1550000 0x0 0x10000>,
				<0x0 0x40000000 0x0 0x4000000>;
			reg-names = "QuadSPI", "QuadSPI-memory";
			interrupts = <0 99 0x4>;
			clock-names = "qspi_en", "qspi";
			clocks = <&clockgen 4 0>, <&clockgen 4 0>;
			status = "disabled";
		};

		esdhc: esdhc@1560000 {
			compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
			reg = <0x0 0x1560000 0x0 0x10000>;
			interrupts = <0 62 0x4>;
			clock-frequency = <0>;
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			big-endian;
			bus-width = <4>;
		};

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		ddr: memory-controller@1080000 {
			compatible = "fsl,qoriq-memory-controller";
			reg = <0x0 0x1080000 0x0 0x1000>;
			interrupts = <0 144 0x4>;
			big-endian;
		};

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		tmu: tmu@1f00000 {
			compatible = "fsl,qoriq-tmu";
			reg = <0x0 0x1f00000 0x0 0x10000>;
			interrupts = <0 33 0x4>;
			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
			fsl,tmu-calibration = <0x00000000 0x00000026
					       0x00000001 0x0000002d
					       0x00000002 0x00000032
					       0x00000003 0x00000039
					       0x00000004 0x0000003f
					       0x00000005 0x00000046
					       0x00000006 0x0000004d
					       0x00000007 0x00000054
					       0x00000008 0x0000005a
					       0x00000009 0x00000061
					       0x0000000a 0x0000006a
					       0x0000000b 0x00000071

					       0x00010000 0x00000025
					       0x00010001 0x0000002c
					       0x00010002 0x00000035
					       0x00010003 0x0000003d
					       0x00010004 0x00000045
					       0x00010005 0x0000004e
					       0x00010006 0x00000057
					       0x00010007 0x00000061
					       0x00010008 0x0000006b
					       0x00010009 0x00000076

					       0x00020000 0x00000029
					       0x00020001 0x00000033
					       0x00020002 0x0000003d
					       0x00020003 0x00000049
					       0x00020004 0x00000056
					       0x00020005 0x00000061
					       0x00020006 0x0000006d

					       0x00030000 0x00000021
					       0x00030001 0x0000002a
					       0x00030002 0x0000003c
					       0x00030003 0x0000004e>;
			#thermal-sensor-cells = <1>;
		};

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		qman: qman@1880000 {
			compatible = "fsl,qman";
			reg = <0x0 0x1880000 0x0 0x10000>;
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			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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			memory-region = <&qman_fqd &qman_pfdr>;
		};

		bman: bman@1890000 {
			compatible = "fsl,bman";
			reg = <0x0 0x1890000 0x0 0x10000>;
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			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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			memory-region = <&bman_fbpr>;
		};

		bportals: bman-portals@508000000 {
			ranges = <0x0 0x5 0x08000000 0x8000000>;
		};

		qportals: qman-portals@500000000 {
			ranges = <0x0 0x5 0x00000000 0x8000000>;
		};

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		dspi0: spi@2100000 {
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			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <0 64 0x4>;
			clock-names = "dspi";
			clocks = <&clockgen 4 0>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

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		dspi1: spi@2110000 {
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			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2110000 0x0 0x10000>;
			interrupts = <0 65 0x4>;
			clock-names = "dspi";
			clocks = <&clockgen 4 0>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		i2c0: i2c@2180000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2180000 0x0 0x10000>;
			interrupts = <0 56 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			dmas = <&edma0 1 39>,
			       <&edma0 1 38>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		i2c1: i2c@2190000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2190000 0x0 0x10000>;
			interrupts = <0 57 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		i2c2: i2c@21a0000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21a0000 0x0 0x10000>;
			interrupts = <0 58 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		i2c3: i2c@21b0000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21b0000 0x0 0x10000>;
			interrupts = <0 59 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		duart0: serial@21c0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0500 0x0 0x100>;
			interrupts = <0 54 0x4>;
			clocks = <&clockgen 4 0>;
		};

		duart1: serial@21c0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0600 0x0 0x100>;
			interrupts = <0 54 0x4>;
			clocks = <&clockgen 4 0>;
		};

		duart2: serial@21d0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0500 0x0 0x100>;
			interrupts = <0 55 0x4>;
			clocks = <&clockgen 4 0>;
		};

		duart3: serial@21d0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0600 0x0 0x100>;
			interrupts = <0 55 0x4>;
			clocks = <&clockgen 4 0>;
		};

		gpio1: gpio@2300000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <0 66 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@2310000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <0 67 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@2320000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2320000 0x0 0x10000>;
			interrupts = <0 68 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@2330000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2330000 0x0 0x10000>;
			interrupts = <0 134 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
		uqe: uqe@2400000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,qe", "simple-bus";
			ranges = <0x0 0x0 0x2400000 0x40000>;
			reg = <0x0 0x2400000 0x0 0x480>;
			brg-frequency = <100000000>;
			bus-frequency = <200000000>;
			fsl,qe-num-riscs = <1>;
			fsl,qe-num-snums = <28>;

			qeic: qeic@80 {
				compatible = "fsl,qe-ic";
				reg = <0x80 0x80>;
				#address-cells = <0>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			};

			si1: si@700 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,ls1043-qe-si",
						"fsl,t1040-qe-si";
				reg = <0x700 0x80>;
			};

			siram1: siram@1000 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "fsl,ls1043-qe-siram",
						"fsl,t1040-qe-siram";
				reg = <0x1000 0x800>;
			};

			ucc@2000 {
				cell-index = <1>;
				reg = <0x2000 0x200>;
				interrupts = <32>;
				interrupt-parent = <&qeic>;
			};

			ucc@2200 {
				cell-index = <3>;
				reg = <0x2200 0x200>;
				interrupts = <34>;
				interrupt-parent = <&qeic>;
			};

			muram@10000 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "fsl,qe-muram", "fsl,cpm-muram";
				ranges = <0x0 0x10000 0x6000>;

				data-only@0 {
					compatible = "fsl,qe-muram-data",
					"fsl,cpm-muram-data";
					reg = <0x0 0x6000>;
				};
			};
		};

675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
		lpuart0: serial@2950000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2950000 0x0 0x1000>;
			interrupts = <0 48 0x4>;
			clocks = <&clockgen 0 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart1: serial@2960000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2960000 0x0 0x1000>;
			interrupts = <0 49 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart2: serial@2970000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2970000 0x0 0x1000>;
			interrupts = <0 50 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart3: serial@2980000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2980000 0x0 0x1000>;
			interrupts = <0 51 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart4: serial@2990000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2990000 0x0 0x1000>;
			interrupts = <0 52 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart5: serial@29a0000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x29a0000 0x0 0x1000>;
			interrupts = <0 53 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		wdog0: wdog@2ad0000 {
			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
			reg = <0x0 0x2ad0000 0x0 0x10000>;
			interrupts = <0 83 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "wdog";
			big-endian;
		};

		edma0: edma@2c00000 {
			#dma-cells = <2>;
			compatible = "fsl,vf610-edma";
			reg = <0x0 0x2c00000 0x0 0x10000>,
			      <0x0 0x2c10000 0x0 0x10000>,
			      <0x0 0x2c20000 0x0 0x10000>;
			interrupts = <0 103 0x4>,
				     <0 103 0x4>;
			interrupt-names = "edma-tx", "edma-err";
			dma-channels = <32>;
			big-endian;
			clock-names = "dmamux0", "dmamux1";
			clocks = <&clockgen 4 0>,
				 <&clockgen 4 0>;
		};

		usb0: usb3@2f00000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x2f00000 0x0 0x10000>;
			interrupts = <0 60 0x4>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
760
			snps,dis_rxdet_inp3_quirk;
761
			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
762
			status = "disabled";
763
764
765
766
767
768
769
770
		};

		usb1: usb3@3000000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x3000000 0x0 0x10000>;
			interrupts = <0 61 0x4>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
771
			snps,dis_rxdet_inp3_quirk;
772
			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
773
			status = "disabled";
774
775
776
777
778
779
780
781
		};

		usb2: usb3@3100000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x3100000 0x0 0x10000>;
			interrupts = <0 63 0x4>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
782
			snps,dis_rxdet_inp3_quirk;
783
			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
784
			status = "disabled";
785
786
787
		};

		sata: sata@3200000 {
788
			compatible = "fsl,ls1043a-ahci";
789
790
791
			reg = <0x0 0x3200000 0x0 0x10000>,
				<0x0 0x20140520 0x0 0x4>;
			reg-names = "ahci", "sata-ecc";
792
793
			interrupts = <0 69 0x4>;
			clocks = <&clockgen 4 0>;
794
			dma-coherent;
795
796
797
		};

		msi1: msi-controller1@1571000 {
798
			compatible = "fsl,ls1043a-msi";
799
800
801
802
803
804
			reg = <0x0 0x1571000 0x0 0x8>;
			msi-controller;
			interrupts = <0 116 0x4>;
		};

		msi2: msi-controller2@1572000 {
805
			compatible = "fsl,ls1043a-msi";
806
807
808
809
810
811
			reg = <0x0 0x1572000 0x0 0x8>;
			msi-controller;
			interrupts = <0 126 0x4>;
		};

		msi3: msi-controller3@1573000 {
812
			compatible = "fsl,ls1043a-msi";
813
814
815
816
817
			reg = <0x0 0x1573000 0x0 0x8>;
			msi-controller;
			interrupts = <0 160 0x4>;
		};

818
		pcie1: pcie@3400000 {
819
			compatible = "fsl,ls1043a-pcie";
820
821
822
823
824
825
826
827
828
			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 118 0x4>, /* controller interrupt */
				     <0 117 0x4>; /* PME interrupt */
			interrupt-names = "intr", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
829
			dma-coherent;
830
			num-viewport = <6>;
831
832
833
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
834
			msi-parent = <&msi1>, <&msi2>, <&msi3>;
835
836
837
838
839
840
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
					<0000 0 0 2 &gic 0 111 0x4>,
					<0000 0 0 3 &gic 0 112 0x4>,
					<0000 0 0 4 &gic 0 113 0x4>;
841
			status = "disabled";
842
843
		};

844
		pcie2: pcie@3500000 {
845
			compatible = "fsl,ls1043a-pcie";
846
847
848
849
850
851
852
853
854
			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 128 0x4>,
				     <0 127 0x4>;
			interrupt-names = "intr", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
855
			dma-coherent;
856
			num-viewport = <6>;
857
858
859
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
860
			msi-parent = <&msi1>, <&msi2>, <&msi3>;
861
862
863
864
865
866
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
					<0000 0 0 2 &gic 0 121 0x4>,
					<0000 0 0 3 &gic 0 122 0x4>,
					<0000 0 0 4 &gic 0 123 0x4>;
867
			status = "disabled";
868
869
		};

870
		pcie3: pcie@3600000 {
871
			compatible = "fsl,ls1043a-pcie";
872
873
874
875
876
877
878
879
880
			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 162 0x4>,
				     <0 161 0x4>;
			interrupt-names = "intr", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
881
			dma-coherent;
882
			num-viewport = <6>;
883
884
885
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
886
			msi-parent = <&msi1>, <&msi2>, <&msi3>;
887
888
889
890
891
892
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
					<0000 0 0 2 &gic 0 155 0x4>,
					<0000 0 0 3 &gic 0 156 0x4>,
					<0000 0 0 4 &gic 0 157 0x4>;
893
			status = "disabled";
894
		};
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916

		qdma: dma-controller@8380000 {
			compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
			reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
			      <0x0 0x8390000 0x0 0x10000>, /* Status regs */
			      <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "qdma-error", "qdma-queue0",
				"qdma-queue1", "qdma-queue2", "qdma-queue3";
			dma-channels = <8>;
			block-number = <1>;
			block-offset = <0x10000>;
			fsl,dma-queues = <2>;
			status-sizes = <64>;
			queue-sizes = <64 64>;
			big-endian;
		};

917
918
919
920
921
922
923
924
925
926
927
928
929
		rcpm: power-controller@1ee2140 {
			compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
			reg = <0x0 0x1ee2140 0x0 0x4>;
			#fsl,rcpm-wakeup-cells = <1>;
		};

		ftm_alarm0: timer@29d0000 {
			compatible = "fsl,ls1043a-ftm-alarm";
			reg = <0x0 0x29d0000 0x0 0x10000>;
			fsl,rcpm-wakeup = <&rcpm 0x20000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
		};
930
931
	};

932
933
934
935
936
937
938
	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

939
};
940
941
942

#include "qoriq-qman-portals.dtsi"
#include "qoriq-bman-portals.dtsi"